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SYSTEM AND METHOD FOR THE OPTIMIZATION OF WORD WIDTHS OF DIGITAL CIRCUITS BY MEANS OF BIT-TRUE SIMULATIONS

Description

The calculation of the optimal word sizes (number of bits of each variable or signal, which minimize the cost of the circuit while maintaining the required level of quality) is one of the most important stages in the design of a specific application digital circuit. A good optimization allows to reduce area and consumption, and at the same time increase the process speed. However, it is a complex problem that takes a long time to calculate. The present invention enables the optimization process to be accelerated by several orders of magnitude. In this way, circuits that required unaffordable time for their optimization using traditional methods, can now be addressed in a reasonable time.

 

Advantages

Among the advantages of this invention are: - It allows reducing the design time of digital circuits. - For a given time, it allows greater optimization (in area, consumption and speed) of complex circuits than traditional optimization methods.

 

Uses and Applications

This invention is framed in the field of Information Technology and Telecommunications (ICT) and is applicable for the optimization of application-specific digital circuits for both ASIC design and FPGAs, for example: digital signal processing (DSPs), communications, audio, video, graphic processing, simulation of physical systems, industrial control, home automation, automotive, neural networks, robotics, etc.

 

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Patent Number

ES2562072B1  Expediente

 

Applicants

Universidad De Málaga, Fundación Universitaria San Pablo Ceu

 

Inventors

Francisco Javier Hormigo Aguilar, Gabriel Caffarena Fernández, José Manuel García Chico

 

Filing Date

18/06/2015 

Protection Level: National (Spain)

Processing Status: Spanish patent

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